Along with the development of semiconductor packaging technologies, different types of semiconductor devices have been produced. Ball Grid Array (BGA) package adopts an advanced type of the semiconductor packaging technology which is characterized in the use of a substrate whose front side is mounted with a semiconductor chip and whose back side is mounted with a grid array of solder balls using self-alignment techniques. Thus, more input/output (I/O) connections can be accommodated on the same unit area of a semiconductor chip carrier to meet requirements for the semiconductor chip of high integration, so that an entire package unit is bonded and electrically connected to an external printed circuit board via the solder balls.
However, fabrication process of the semiconductor device generally involves fabricating chip carriers such as a substrate or a lead frame in chip carrier manufacturing followed by subsequent processes of chip-mounting, molding and solder ball implantation in semiconductor packaging to eventually achieve desired electronic performances of the semiconductor device. The actual fabrication processes of the semiconductor device are complicated and integration of interface can be difficult since the semiconductor device is fabricated by different industries (including the chip carrier manufacturing and the semiconductor packaging). Additionally, if the client terminal wishes to design with altered functions, the level of integration and alteration involved would be more complicated; thereby flexibility and economical efficiency for desired modification are not met.
Moreover, for the general fabrication process of a flip-chip based semiconductor device, an under bump metallurgy (UBM) layer is formed on a conductive pad of a chip within a wafer for accommodating a metal bump after fabrication of the wafer integrated circuit is completed. Subsequently, the wafer is singulated to produce a plurality of chips by a singulation process and the flip-chip based semiconductor chip is then mounted on and electrically connected to a substrate. In the process of fabricating the UBM structural layer and the metal bump, a passivation layer is firstly formed on a surface of the semiconductor wafer while exposing the conductive pad. An UBM layer comprising multiple layers of metal is formed on the exposed conductive pad by sputtering and electroplating processes. Then, a solder mask layer predefined with a plurality of openings is formed on the passivation layer to expose the UBM layer. Next, a coating process is performed to apply solder material such as Sn/Pb alloy on the exposed UBM layer through the openings of the solder mask layer by screen-printing techniques. The solder is bonded to the UBM layer by a reflow process, followed by removing the solder mask layer. Subsequently, a second reflow process is performed to round up the solder material so as to form the metal bump on the semiconductor wafer, such that the metal bump serves to connect the semiconductor chip and the substrate before semiconductor packaging is performed.
However, the above fabrication is complex and the integration of interface is difficult. Therefore, a circuit board structure for integrating fabrication of the chip carrier and the semiconductor package has been developed. After the wafer integrated circuit process is complete and a conductive structure is formed on the conductive pad of the chip within the wafer, a singulation process is performed to cut the wafer into a plurality of chip units, and the chip units are embedded in the predefined openings of the circuit board. Subsequently, an electroplated metal structure is formed on the conductive structure to electrically connect the chip and the circuit board, so as to provide the circuit board integrated with the semiconductor chip.
FIGS. 1A through to 1I illustrate processes of forming the conductive structure and the electroplated metal structure on the conductive pad of a wafer. Referring to FIG. 1A, a wafer 10 having a plurality of chips 100 is provided, wherein the wafer 10 is completed with integrated circuit fabrication and a patterned passivation layer 11 is formed on a surface of the wafer 10 to expose conductive pads 12 of the chips provided within the wafer. Referring to FIG. 1B, a zincified layer 13 (serving as a catalytic layer) and an electroless-plating nickel layer 14 are formed on the conductive pad 12, such that the nickel layer 14 is effectively adsorbed on the conductive pad 12 to provide an efficient isolation barrier between the conductive pad 12 and subsequently formed copper metal. Referring to FIG. 1C, an impregnant gold layer 15 is formed on the nickel layer 14 to passivate the nickel layer 14 while allowing the subsequently deposited copper metal to be effectively adsorbed thereon. Referring to FIG. 1D, a thick electroless-plating copper layer 16 is formed on the gold layer 15 and the wafer 10 is singulated to produce a plurality of chips 100. Then, the chips 100 are embedded in predefined openings 102 of a circuit board 101. Referring to FIG. 1E, an insulating layer 17 such as ABF (Ajinomoto build-up film (commercial name), produced by Ajinomoto Co., Inc. Japan) is formed on a surface of the circuit board 101 embedded with the chips 100. FIG. 1E illustrates only one conductive pad 12 of the circuit board 101 shown in FIG. 1D. Referring to FIG. 1F, a part of the insulating layer 17 and thick copper layer 16 corresponding to the conductive pad 12 of the chip is removed using laser-drilling techniques to form an opening 170, such that the thick copper layer 16 that remains in the opening 170 serves as an adhesion layer for subsequent metal deposition. The opening 170 is then subjected to a de-smear process. Referring to FIG. 1G, a conductive layer 18 is formed over the insulating layer 17 and the opening 170. The conductive layer 18 is made by electroplating with a palladium layer (serving as a catalytic layer) followed by an electroless plating process to form the copper layer. Referring to FIG. 1H, a patterned resist layer 19 having a plurality of openings 190 is formed on the conductive layer 18 to expose a part of the conductive layer 18 corresponding to the conductive pad of the chip. Referring to FIG. 11, an electroplated metal structure 191 such as copper metal is formed within the opening 190 of the resist layer 19 by an electroplating process to subsequently provide a conduction path between the chip and the circuit board.
However, during the formation of the conductive structure on the conductive pad of the chip, it is necessary to form the nickel layer and the thick copper layer in sequence by the electroless plating process, which requires a long fabrication time and a large fabrication cost. This leads to remarkable drop in fabrication efficiency. Moreover, a gold layer is usually deposited prior to the formation of the thick copper layer, which deposition further complicates the fabrication process and increases the fabrication cost.